The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having passive energy storage elements thereon.
Conventional integrated circuit device fabrication methods have typically not included techniques to form high quality factor (Q) inductors on integrated circuit substrates. For microwave and wireless communication applications, it may be advantageous to integrate high-Q inductors on bulk silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) substrates. The quality factor (Q) is expressed by the equation Q=xcfx89L/R, where xcfx89 represents resonant frequency, L represents inductance and R represents resistance. Attempts to fabricate high-Q inductors have typically been limited by the fact that conventional wiring interconnect technologies frequently result in conductors and vias having relatively high series resistance when summed together along the length of the inductor. Moreover, integrated circuit inductors may generate magnetic fields that are strongly coupled to an underlying semiconductor substrate, which may act as a lossy conductor having a large skin depth. As will be understood by those skilled in the art, such strong coupling may generate eddy currents within the substrate and these currents act in opposition to currents established in the inductor. Accordingly, strong coupling between an inductor and a semiconductor substrate may operate to reduce the inductance L of the inductor and cause energy loss.
Attempts have been made to fabricate integrated circuit inductors having high quality factors. One such attempt is disclosed in U.S. Pat. No. 6,114,937 to Burghartz et al., which is entitled xe2x80x9cIntegrated Circuit Spiral Inductor.xe2x80x9d In particular, the ""937 patent discloses a spiral inductor having a spiral metal coil that is deposited into a trench formed in a dielectric layer, which extends over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic core lines surrounded by the metal spiral coil (see, e.g., ""937 patent, FIG. 13). Another attempt is disclosed in U.S. Pat. No. 5,446,311 to Ewen et al., which is entitled xe2x80x9cHigh-Q Inductors in Silicon Technology Within Expensive Metallization.xe2x80x9d In particular, the ""311 patent discloses an inductor structure that is formed using multiple metallization levels in a conventional integrated circuit technology in which inductor turns utilize the multiple levels to reduce the inductor resistance (see, e.g., ""311 patent, FIG. 3). U.S. Pat. Nos. 5,892,425, 5,936,299, 6,160,303 and 6,348,391 also disclose a variety of integrated circuit inductors.
Notwithstanding these attempts to develop inductors that are suitable for fabrication on integrated circuit substrates, there continues to be a need for inductors having high quality factors. There also continues to be a need for inductors that may be fabricated using process techniques that yield inductors having highly reproducible quality factors.
Integrated circuit inductors according to embodiments of the present invention achieve high quality factors by replacing a single conductive strand having a first cross-sectional area with a plurality of conductive strands having a combined second cross-sectional area that is smaller than the first cross-sectional area and a combined periphery that is greater than a periphery of the single conductive strand. The dimensions of the plurality of the conductive strands are greater than a skin depth at a desired operating frequency. In particular, embodiments of the present invention include a plurality of strands of conductive traces (e.g., metal traces) that are electrically coupled in parallel and extend side-by-side across an integrated circuit substrate. This substrate may be, for example, a bulk semiconductor substrate (e.g., silicon chip), an silicon-on-insulator (SOI) substrate or a silicon-on-sapphire (SOS) substrate. Each of the plurality of strands also includes a plurality of crossing strand segments that enable the respective strand to be repeatedly transposed from one side of the plurality of strands to another side of the plurality of strands without electrical interruption. In some embodiments, the plurality of strands extend side-by-side in a horizontal plane that is at least substantially parallel to a surface of the integrated circuit substrate. In these embodiments, the crossing strand segments may be treated as crossover/under strand segments. In other embodiments, the plurality of strands extend side-by-side in a vertical plane that is at least substantially orthogonal to a surface of said integrated circuit substrate. According to preferred aspects of these embodiments, the plurality of strands are electrically insulated from each other over at least a majority of their length.
Each of the plurality of strands of conductive traces may include a corresponding plurality of primary strand segments that are electrically linked together end-to-end by a corresponding plurality of the crossing strand segments. The primary strand segments and the crossing strand segments may be formed on different levels of metallization (e.g., metal N and metal N+1 in a process having at least two levels of metallization). To provide electrical continuity, the primary strand segments and the crossing strand segments for each respective strand are electrically coupled together by conductive vias that extend through an electrically insulating layer disposed between the different levels of metallization.
In other embodiments, an inductor having a high quality factor includes an integrated circuit substrate and a plurality of first strands of conductive traces that are electrically coupled in parallel and extend side-by-side across the integrated circuit substrate. Each of the plurality of first strands includes a respective plurality of crossing strand segments at a first level of metallization that enable the respective first strand to be repeatedly transposed from one side of the plurality of first strands to another side of the plurality of first strands without electrical interruption. Each of the plurality of first strands also includes a corresponding plurality of primary strand segments that are electrically linked together end-to-end by a corresponding plurality of the crossing strand segments. The crossing and primary strand segments associated with each of the plurality of first strands may be electrically coupled together by conductive vias that extend through an electrically insulating layer disposed between the different levels of metallization. A plurality of second strands of conductive traces are also provided. These second strands are electrically coupled in parallel and extend side-by-side across the integrated circuit substrate. In some embodiments, these second strands may extend directly above or below the first strands. Each of the plurality of second strands includes a respective plurality of jumper strand segments at a second level of metallization that enable the respective second strand to electrically jump a plurality of the crossing strand segments associated with the plurality of first strands. These jumper strand segments may be contiguous with the primary strand segments that make up the first strands.
According to still further embodiments of the present invention, an inductor includes a semiconductor substrate and a plurality of strands of conductive traces that are electrically coupled in parallel and extend side-by-side across the semiconductor substrate in a horizontal plane that is at least substantially parallel to a surface of the semiconductor substrate. In these embodiments, each of the plurality of strands includes a plurality of crossing strand segments that enable the respective strand to be repeatedly transposed from one side of the plurality of strands to another side of the plurality of strands without electrical interruption. To reduce lossy eddy currents in the substrate, a plurality of alternating N-well and P-well regions are disposed side-by-side therein. These well regions, which extend underneath the plurality of strands, are preferably elongate regions that extend in a direction at least substantially orthogonal to the plurality of strands.